Electric copper plating liquid and process for manufacturing semiconductor integrated circuit device using same

ABSTRACT

An object of the present invention is to improve the reliability and the yield of production of semiconductor integrated circuit devices by filling copper in the inside of features having a high aspect ratio for forming multi-layer interconnections composed of a plurality of interconnection layers which are connected to one another and to a copper electroplating bath suitable therefor. In the present invention, when the features are filled with copper, the use of a copper electroplating bath with an addition of cyanine dyes, for example, indolium compounds allows the copper plating to proceed preferentially from the bottoms of the features.

BACKGROUND OF THE INVENTION

The present invention relates to a copper plating bath, moreparticularly, to a copper electroplating liquid to be used for fillingcopper in fine openings in insulating layers by electroplating, and aprocess for manufacturing a semiconductor integrated device withmulti-layer interconnections formed using the same.

There have been conventionally used aluminum or aluminum-copper alloysas materials for use in interconnections in semiconductor devices. Asinterconnections are micronised with more highly integrated LSI, thedelay of signal transmission due to an increase in resistance andcapacitance of the interconnections and reduced reliability due toelectromigration become a problem. In order to overcome this problem,there has been proposed a method of reducing the resistance ofinterconnections by making them with metals having a low resistance suchas gold, silver and copper. Among them, copper is expected to be asubstitute for aluminum and alloys thereof.

As opposed to aluminum, copper can not produce a compound having a highvapor pressure so that it is difficult to form fine patterns by dryetching. For this reason, there has been employed a technique (called asDamascene method) where trenches and vias are first formed in insulatinglayers in place corresponding to the patterns of interconnections, andthen they are filled with copper.

Generally all the surfaces of a substrate including features therein aremetallized and then excess metals are removed to form interconnections.

More practically, when interconnections are produced, adiffusion-inhibiting layer (barrier layer) and a copper seed layer areformed on the surfaces of an insulating interlayer having trenches andvias formed therein by sputtering and then copper is filled in thetrenches and vias by electroplating with a seed layer being as anelectron transmitting layer. Materials to be used for the barrier layerinclude high melting point metals such as tantalum, tungsten and thelike, and alloys thereof and nitrides such as titanium nitride, tantalumnitride and the like.

Techniques for filling the features include physical vapor deposition(PVD) such as sputtering, chemical vapor deposition (CVD), and plating.The PVD method is poor in coverage with metals on the sides of thefeatures making their aspect ratio higher (that is, making the featuresthinner and deeper), which may form voids in the filled metals. The CVDmethod is relatively good in coverage, but it suffers from high costs ofsource materials. The plating is lower in cost as compared with othermethods and excellent in filling property. Therefore, it has attractedmuch interest. Particularly electroplating is excellent in fillingproperty, provides a high throughput, and effective to mass production.Therefore, it is most promising as a method for filling features.

For example, Japanese Patent KOKAI No. Hei 11-26394 discloses a processfor filling trenches by electroplating after forming an iodine coatinglayer on a seed layer.

Japanese Patent KOKAI No. Hei 11-97391 discloses a process for producinginterconnections by electroplating with pulse current in a plating bathwithout additives.

Japanese Patent KOKAI No. Hei 11-310896 discloses a process forproducing interconnections in a plating bath containing little supportelectrolyte.

Japanese Patent Kokai No. 2000-248397 discloses a process for fillingtrenches by adding a polymeric surfactant, a sulfur-based saturatedorganic compound and an organic dye compound to a plating bath.

As described above, though various processes have been studied to fillfine features with metals by using electroplating, each of them has aproblem.

The process of Japanese Patent KOKAI No. Hei 11-26394 provides conformaldeposit of metal by plating. If there are irregularities on the surfaceof a seed layer, the deposits on the raised sites may come to contactwith adjacent deposits on the sides of the features as the platingproceeds, resulting in formation of voids. Even when the plated film hasan appearance of a flat surface due to iodine, seam may be formed in thecentral portions of the features because the surface is not perfectlyplat.

In the process of Japanese Patent KOKAI No. Hei 11-97391, the use ofpulse current can make a diffusion layer thinner, which may allowuniform deposits on the fine features to be expected. However, theconformal deposition by this process may generate voids similarly tothose as described above. It is difficult with the plating bathcontaining no additives to form flat films because the films to bedeposited under plating grow reproducing the irregularities on thesurface of the primer seed layer.

The process of Japanese Patent KOKAI No. Hei 11-310896 increases anamount of copper diffused into fine features by significantly reducingan amount of support electrolyte in a plating bath. However, even whensufficient amount of copper is supplied, conformal depositions occur inthe features, resulting in formation of voids and seams.

In the process disclosed in Japanese Patent Kokai No. 2000-248397, theorganic dye compound such as Absorber Dye ADI or Cy5 is added to theplating bath so as to attain levelling function which smoothes thecopper surface. Absorber Dye ADI and Cy5 comprise an anionic compoundhaving 2 or more of sulfonic groups. Such a compound is scarecelyadsorbed on the surface in the plating step. Therefore, it is hard togrow plating preferentially from the bottoms, which is accomplished by areaction of an additive described below.

Thus, it is difficult to fill completely the features having a highaspect ratio by the conventional electroplating process as describedabove. The interconnections having voids and seams therein suffer fromincrease of wiring resistivity, delay of the transmission of electricsignals and the like. Therefore, there has been a need for a techniquewhich allows such fine features to be completely filled.

As trenches were filled with copper by a bottom-up-filling technique,i.e., a technique of facilitating copper plating on the bottom oftrenches as described in the report by Mr. Reid, titled “CopperElectrodeposition for IC interconnect Formation” in AdvancedMetallization Conference (ADMETA), Oct. 13, 1999, pp. 65-102, studies onits mechanism and plating baths suitable for it have been intensivelymade.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a copperelectroplating bath suitable for filling copper in features having ahigh aspect ratio with high reproducibility.

It is another of the present invention to provide a copperelectroplating bath suitable for filling copper in features having ahigh aspect ratio without generating voids and seams with highreproducibility.

It is still another of the present invention to provide a semiconductorintegrated circuit device having a high interconnection density in theinterconnection layers having a high electromigration resistance wherefine features have been filled with copper, i.e., without existing voidsand seams, using such a plating bath as above.

The present invention will be summarized under.

In the present invention, an additive is added to a copperelectroplating bath, said additive suitable to allow copper plating toproceed preferentially from the bottoms of features such as trenches andvias having a high aspect ratio which have been formed on the surfacesof a substrate.

The copper electroplating bath of the present invention comprises asolution containing copper ions and electrolyte(s) with an addition of,for example, cyanine dye.

In an embodiment of the copper electroplating bath of the presentinvention, the solution containing copper ions and electrolyte(s)contains as an additive at least one of cyanine dyes represented by, forexample, the following general formula (I):

where X⁻ is an anion, and n is 0, 1, 2, or 3 (abbreviated as n=0 to 3hereunder).

In another embodiment of the copper electroplating bath according to thepresent invention, the solution containing copper ions andelectrolyte(s) is characterized by having an indolium compound addedthereto.

In a preferred embodiment, the copper electroplating bath may contain atleast one or more of polyethers, organic sulfur compounds and halideions as further additives.

The process for producing a semiconductor integrated circuit devicesaccording to the present invention comprises providing an insulatinglayer having openings on the top of the major surface of a semiconductorwafer which has a plurality of circuit element areas formed therein,depositing a barrier layer and a seed layer on the bottom and the sidesurfaces of the openings and on the top surface of the insulating layer,and filling the inside of the openings with copper without forming anyvoids and seams by electroplating with the copper electroplating bath asdescribed above to from a interconnection layer. The process is capableof producing a high packing density LSI having an excellent reliabilitywith high reproducibility.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, 1C, and 1D show a cross-sectional view of a major part ofan interconnect structure at each step of the process for the productionthereof in an Example according to the present invention, respectively.

FIGS. 2A, 2B, 2C, and 2D show a cross-sectional view of a major part ofan interconnect structure at each step of the process for the productionthereof in another Example according to the present invention,respectively.

FIG. 3 shows a cross-sectional view of a major part of an interconnectstructure showing how a copper film is allowed to grow by the platingaccording to the present invention.

FIG. 4 shows a cross-sectional view of a major part of an interconnectstructure in a Comparative Example to demonstrate the effect of thepresent invention.

FIG. 5 shows a cross-sectional view of a major part of aninterconnection structure showing how a copper film is allowed to growby the plating in a Comparative Example to demonstrate the effect of thepresent invention.

In the drawings, each reference number designates a part as follows:

-   1: Silicon substrate; 2: Insulating layer; 3: Via; 4: Barrier layer;    5: Seed layer; 6: Copper electroplated layer; 7: Trench; 8:    Insulating layer; 9, 11 and 12: Copper layer; 13: Void.

DETAILED DESCRIPTION OF THE INVENTION

As described above, metals which may be used in filling fine featureswith a low resistance metal by electroplating include gold, silver andcopper. These metals may diffuse into adjacent insulating layers andsemiconductor layers to deteriorate characteristic properties of circuitelements. Therefore, the diffusion must be prevented by providing abarrier layer under the metal layer. Electroconductive materials whichcan function as barrier include metal nitrides such as titanium nitride,tungsten nitride, tantalum nitride, and high melting point metals suchas tantalum and tungsten and alloys thereof. These barrier layers arealso disposed sequentially to the surfaces of the insulating layershaving the trenches and the vias as well as the inside of thereof.

The barrier layer which may be made of any one of metal nitrides andhigh melting point metals and alloys thereof has a relatively highresistance and may produce a relatively stable oxide on the surface, sothat it is difficult to electroplate directly the surface of the barrierlayer. For this reason, a seed layer as an electron transmitting layer,e.g., a copper film is further formed on the barrier layer using PVD,CVD, or electroless deposition process.

Next, according to the subject of the present invention, a copper iselectroplated on the seed layers present even on the inner surfaces ofthe feature by copper electroplating to fill the inside of the featurewith copper. The characteristics of the copper film are very sensitivelydepending upon the configuration of the seed layer and the thickness ofthe film.

For example, when the seed layer is discontinuous, the plating rate atthe sites without any seed layer is very slow or produce no platingresulting in generation of voids. When the seed layer is not uniform inthickness or has irregularities on the surface, uniformity of thegrowing copper film is inhibited, that is, the thickness of copper filmbecome not uniform during copper electroplating resulting in theformation of seams, i.e., seam like boundary in the copper film fillingthe inside of the feature.

The presence of such voids and seams may cause the confinement ofplating bath components, air and moisture at the sites to reduce thereliability of the resulting semiconductor integrated circuit deviceshaving highly packed fine interconnections. Therefore, the seed layermust be uniformly produced throughout the surfaces of the insulatinglayer and the inside of the feature. A non-negligible variation of theseed layer in the LSI having quite a lot of openings has an influence onthe final proportion of good products, i.e., yield.

Even when a seed layer is formed throughout the surfaces, preferentialgrowth of electroplated copper deposit in the openings of the featuremay close off the feature. As a result, voids having plating bathremained therein are produced. When a copper grows conformally byelectroplating, the plated film can not perfectly be flat so that voidsand seams are inevitably formed in the central portion.

In order to fill the features with seamless copper, therefore, it isnecessary to allow copper electroplating deposit to grow preferentiallyfrom the bottoms of the features. Moreover, as described above, it mustbe reproducibly conducted without being affected by fluctuation of thecharacteristics of the seed layer.

The present inventors have found that electroplating deposits can begrown preferentially from the bottoms of the features by using aspecific additive with good reproducibility as described above. Theadditive is a material which suppresses the electroplating reaction andis consumed as the electroplating reaction proceeds. That is, thecommencement of the electroplating reaction reduces the concentration ofthe additive on the surfaces where the reaction is taking place. If thediffusion rate of the additive is lower than the rate of the additivereaction, the diffusion of the additive controls the electroplatingreaction. Therefore, an extent of the suppression of reaction depends onthe amount of the additive to be supplied to the surfaces throughdiffusion.

For this reason, there may be a difference in the amount of the additiveto be supplied through diffusion between the regions in the vicinity ofthe openings of the features and the bottoms of the features. Theadditive is smoothly supplied in the vicinity of the openings, resultingin the suppression of the electroplating reaction. On the other hand,inside the features, the additive tends to react into a material havingno effect of suppressing the electroplating reaction before it reachesthe bottoms, so that the amount of the additive is reduced in thebottoms. Therefore, the electroplating reaction at the bottoms is muchless suppressed as compared with that around the openings. That is, lessamount of the additive having an effect of suppressing the reaction issupplied to the bottoms, so that the electroplating proceedspreferentially from the bottoms.

If the additive has a very low rate of reaction, or if the rate ofdiffusion is very high, a sufficient amount of the additive may besupplied to the bottoms of the features. Therefore, the difference insuppression is reduced between the bottoms and the openings. If theadditive has a very high rate of reaction, or if the rate of diffusionis very low, little supplement of the additive may be effected to theopenings of the features. The difference in suppression is again reducedbetween the bottoms and the openings. Therefore, preferably the additiveshould be of a molecule which has a rate of diffusion and a rate ofreaction in such appropriate ranges as producing a difference inconcentration between the openings and the bottoms of the features.Consequently, this can be an extremely effective measure to theinfluence of the fluctuation of the characteristics of theaforementioned seed layer.

Materials useful for such an additive include2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-methyl]-1,3,3-trimethyl-3H-indoliumperchlorate,2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indoliumchloride,2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indoliumiodide, and2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indoliumiodide. They should be preferably used in a concentration of about 1 to15 mg/liter (which may be abbreviated as mg/L hereunder). The additiveconcentration outside this range may be effective as additive. If theconcentration is lower than 1 mg/L, resulting effects may beinsufficient, while if the concentration is higher than 15 mg/L, theconcentration of impurities in the copper may possibly increased.

After the copper electroplating, excess portions of metal layers on theinsulating layer (that is, the electroplated copper layer, the seedlayer, and the barrier layer) are removed by CMP. At this point, sincethe uniformity in film thickness and the film flatness are required onthe wafer, it is preferred to further add one or more of polyethers,organic sulfur compounds, and halide ions in addition of theaforementioned cyanine dyes to improve the thickness distribution on thewafer.

Such polyethers are preferably polyethylene glycols, polypropyleneglycols, polyoxypropylene glycols having an average molecular weight of1000 to 10,000.

The organic sulfur compounds are preferably 3-mercapto-1-propanesulfonicacid, 2-mercapto ethane sulfonic acid, bis(4-sulfobuthyl)disulfide,bis(3-sulfopropyl)disulfide, bis(2-sulfoethyl)disulfide, orbis(p-sulfophenyl)disulfide.

Description of Preferred Embodiments

The following Examples demonstrate preferred embodiments of the presentinvention.

The copper electroplating bath according to the present invention isused in a range of 15 to 35° C. in order to avoid excessivedecomposition of an additive. A concentration of copper ions of 0.2mol/L or more is preferred and usually used in a range of currentdensity of 0.2 to 3.0 A/dm² (square decimeter). When the copperelectroplating is conducted, preferably the plating bath should bestirred with a pump or air, or the substrate should be rotated orvibrated in order to maintain the supply of the additive constant.

EXAMPLE 1

First, a composition of the copper electroplating bath and a process forelectroplating copper on an interconnection substrate structure usingthe same according to the present invention and a method of evaluationfor them with reference to FIGS. 1A, 1B, and 1C.

i) Preparation of Interconnection Substrate Structure

In order to make it possible to evaluate characteristics of variousplating baths as precisely as possible, basic samples of theinterconnection substrate structure were commonly prepared as follows:

That is, as shown in FIG. 1A, an insulating layer 2 of SiO₂ having athickness of 1.0 μm was formed on the surface of a silicon substrate ofφ 200 mm, and etched by ordinary dry etching to from vias 3 having φ0.25 μm and a depth of 1 μm.

Then, by sputtering, tantalum was deposited on the overall top surfaceto form a barrier layer 4 having a thickness of 50 nm and copper wasdeposited on the barrier layer to form a seed layer 5 having a thicknessof 150 nm. The seed layer 5 was produced at a film formation rate of 200to 400 nm/min using Ceraus ZX-1000, a long distance sputtering apparatusfor sputtering copper (made by ULVAC Co.). FIG. 1B shows across-sectional view of the structure after the copper seed layer wasformed.

ii) Process for Electroplating Copper

There were prepared various plating baths each having a composition asindicated in the following Table 1, and copper was electroplated on thetop surface of the interconnection structure as shown in FIG. 1B to forman electroplated copper 6 as shown in FIG. 1C. The plated substratestructure obtained according to the procedure as described above wasremoved from the copper electroplating bath and washed with distilledwater for 3 minutes. TABLE 1 Composition of Plating Bath PlatingSulfuric Condition Sam- Copper Acid Hydrochloric Type of AdditiveCurrent ple Conc. Conc. Acid Conc. Addi- Conc. Density No. (mol/L)(mol/L) (mol/L) tive (mol/L) (A/dm²) 1 0.30 1.9 0 A-1 10 1.0 2 0.40 2.01.9 × 10⁻³ A-3 8 2.5 3 0.80 1.0 0.9 × 10⁻³ A-2 0.5 1.0 B-1 100 C-1 30 40.30 1.9 1.5 × 10⁻³ A-4 20 2.0 B-2 50 C-4 30 5 0.26 1.9 1.9 × 10⁻³ A-2 10.2 B-2 80 C-3 15 6 0.30 1.9 1.9 × 10⁻³ A-2 10 1.5 B-1 40 C-3 20 7 0.801.0 1.6 × 10⁻³ A-2 15 3.0 B-3 40 C-3 10 8 0.40 1.9 1.9 × 10⁻³ A-1 8 1.0B-4 20 C-2 10 9 0.30 1.9 0 — — 1.0

Sample Nos. 1 to 8 in Table 1 indicate copper electroplating bathsaccording to the present invention, and Sample No. 9 was indicates acopper electroplating bath outside the present invention prepared forcomparison.

Various signs described in the column “Type of Additive” designate thefollowing chemical materials:

A-1:2-[(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-e)-methyl]-1,3,3-trimethyl-3H-indoliumperchlorate.

A-2:2-[3-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1-propenyl]-1,3,3-trimethyl-3H-indoliumchloride.

A-3:2-[5-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3-pentadienyl]-1,3,3-trimethyl-3H-indoliumiodide.

A-4:2-[7-(1,3-Dihydro-1,3,3-trimethyl-2H-indol-2-ylidene)-1,3,5-heptatrienyl]-1,3,3-trimethyl-3H-indoliumiodide.

B-1: Polyethylene glycol (an average molecular weight of 3000).

B-2: Polyethylene glycol (an average molecular weight of 1000).

B-3: Polypropylene glycol (an average molecular weight of 3000).

B-4: Polypropylene glycol (an average molecular weight of 1000).

C-1: 3-mercapto-1-propanesulfonic acid.

C-2: 2-mercapto ethane sulfonic acid.

C-3: bis(3-sulfopropyl)disulfide.

C-4: bis(2-sulfoethyl)disulfide.

Each electroplating was conducted at a current density as indicated inTable 1 for a period of time capable of providing a charge correspondingto the formation of a film thickness of 1.0 μm. When the process ofgrowth of film deposit was to be observed, the electroplating wasconducted for a period of time capable of providing a chargecorresponding to the formation of a film thickness of 0.03 μm.

The temperature was at 24° C. and the total amount of liquid was 20liter in a bath. As anode electrode, phosphorus-containing copper wasused. The electroplating bath was circulated through a filter at a rateof 15 liter/min with an external pump.

iii) Evaluation of Electroplated Copper Film

The cross-section of the plated film was observed by a scanning electronmicroscope (SEM) where the substrate structure after plated (FIG. 1C)was processed with FIB (Focused Ion Beam) and the cross-sections of 100vias were observed. When the process of the growth of copper film to beplated was observed, in the cross-section of the major portion of theinterconnection structure as shown in FIG. 3, the thickness of platedfilm (A) on the surface of the substrate on the way of plating and thethickness of plated film on the bottom of vias (B) were measured and theratio of B/A was calculated. The uniformity in sheet resistance ofplated copper film was evaluated based on measurements at 49 points by afour probe method of the resistivity measurement. Moreover, the test ofelectromigration resistance (EM resistance) was conducted in thefollowing procedure: a direct current was passed through theinterconnections prepared according to the present invention and theresistance was measured with time. The end of the lifetime was definedat the time when the resistance of the interconnections increased by30%. Comparisons of the results obtained under various conditions weremade. The high EM resistance of the copper interconnections improves thedurability of the semiconductor devices themselves. These results aresummarized in Table 2 under. TABLE 2 Evaluation Items Plating BathPlating Uniformity Composition Condition in plane of Conc. of CurrentSheet EM Sample Type of Cyanine bye Density Resistance Presence ofResistance No. Dyes (mg/L) (A/dm²) (%) B/A boid (a.u.) 1 A-1 10 1.0 132.1 No 1.4 2 A-3 8 2.5 17 3.0 No 1.5 3 A-2 0.5 1.0 3 2.8 No 4.2 4 A-4 202.0 5 3.2 No 5.0 5 A-2 1 0.2 4 5.1 No 5.2 6 A-2 10 1.5 4 4.5 No 6.1 7A-2 15 3.0 5 5.3 No 4.9 8 A-1 8 1.0 4 6.1 No 5.4 9 — — 1.0 21 1.0 Yes1.0

The designations of the signs in the column “Type of Cyanine Dye” inTable 2 are the same as those in Table 1. They are reused forconvenience. The B/A is the ratio of the film thickness on the bottomsof the features (B) to that on the surface (A).

The plating bath of Sample No. 9 (comparative) produced voids asdescribed later, while those of Sample Nos. 1 to 8 (present invention)did not produced observable voids and seams after plating, because ofthe addition of cyanine dyes to the plating bath allowing the bottoms ofthe vias to be preferentially plated. Thus, good filling performancecould be achieved. Moreover, the EM resistance of the interconnectionswas also improved. Therefore, it has been found that the semiconductorintegrated circuit devices produced according to the present inventionhave an improved reliability.

Sample Nos. 3 to 8 contained a polyether, an organic sulfur compound andhalide ions in addition to cyanine dye. It has been found that theyachieved a good filling property as well as a good uniformity in filmthickness on the plane of the substrate with good reproducibility as canbe seen from the excellent uniformity in sheet resistance in a range of3 to 5%. Moreover, the EM resistance of the interconnections was alsoimproved. Therefore, it has been found that the semiconductor integratedcircuit devices having an excellent reliability can be produced.

Sample Nos. 5 to 8 made it possible to further facilitate the growth offilm to be preferentially plated on the bottoms (FIG. 3) by renderingthe concentration of cyanine dye appropriate as can be seen from thehigh ratio of B/A in a range of 4.5 to 6.1.

In order to make the effects of the present invention more easilyunderstandable, the present Example 1 will be described with referenceto the comparison with the copper electroplating bath of Sample No. 9(comparative) as shown in Table 1.

With the copper electroplating bath of Sample No. 9 shown on the bottomin Table 1 as a case of using none of the aforementioned additives whichare characteristic of the present invention, copper was plated followingto steps 1A, 1B and 1C shown in the drawings.

The substrate structure after plated was processed with FIB in the samemanner as above and the cross-sections of 100 vias were observed by SEM.As a result, voids were observed in the copper films in the holesindicating that there were produced portions not filled with copper inthe vias as shown in the cross-sectional view thereof in FIG. 4.Moreover, it was confirmed that some of voids became smaller into a seamlike form.

Observation of the process of the growth of copper film to be platedrevealed that all the vias ave a uniform copper film grown inside thefeature as shown in FIG. 5 and that the electroplating did not proceedpreferentially from the bottoms. In this case, the ratio of B/A wascalculated to be 1.0.

The foregoing demonstrate the predominancy of the present invention thatthe vias can be perfectly filled with copper by allowing theelectroplating to proceed preferentially from the bottoms thereof.

EXAMPLE 2

Next, the process for producing a semiconductor integrated circuitdevice having multi-layer interconnections by using the copperelectroplating bath according to the present invention will be describedwith reference to FIG. 1 again.

FIG. 1 shows a cross-sectional view of a major part of a semiconductorintegrated circuit device having a plurality of semiconductor circuitelement areas formed therein (not shown) at each step of the process forthe production of the device. It shows an example where the presentinvention is applied to fill the inside of the features for connecting aplurality of interconnection layers at different levels with copper byelectroplating.

That is, in FIG. 1A, a substrate 1 has an interconnection layer (notshown) which is formed on an insulating layer coating the surface of asilicon wafer of φ 200 mm which has a plurality of semiconductor circuitelement areas (not shown) formed, said inter-connection layer beingconnected to said plurality of semiconductor circuit element areas. Aninsulating interlayer 2 of SiO₂ or the like having a thickness of 1 μmwas deposited on the top surface of the substrate. Said interlayer hasthe bottom surface in contact with the top surface of saidinterconnection layer (that is, it terminates at the contact) and it wasprovided with vias 3 having such a high aspect ratio as having φ 0.25 μmand a depth of 1 μm for connecting between interconnection layers. Atthe bottoms of the vias, said interconnection layer is exposed.

Next, as described in Example 1 and as shown in FIG. 1B, a barrier layer4 is deposited continuously on the top surface of the insulating layer 2and a seed layer 5 is deposited on the barrier layer. The exposedportions of the surface of the interconnection layer at the bottoms ofthe holes are covered with the barrier layer 4 to be electricallyconnected.

Then as shown in FIG. 1C, a copper layer 6 is plated on the surface ofthe seed layer 5 using the copper electroplating bath according to thepresent invention as described above, to fill the vias 3 with thecopper.

The substrate which was plated by the process as described above wasremoved from the copper electroplating bath and washed with distilledwater for 3 minutes. Then it was processed with FIB and thecrosssections of 100 vias were observed by SEM. As a result, it wasfound that voids or seams were not observed and the vias 3 wereperfectly filled with copper.

Next, as shown in FIG. 1D, chemical and mechanical polishing waseffected to remove the metal 6 deposited by the electroplating. Thechemical mechanical polishing was performed by using a chemicalmechanical polishing apparatus, CMP Apparatus AVANT Model 1472 (made bySpeedFam-IPEC Co.) with alumina dispersion grains containing 1 to 2%hydrogen peroxide and a pad (IC-1000 made by Rodel Co.). The polishingwas conducted to reach the insulating layer under a pressure of 150g/cm². As a result, no separation occurred at each boundary. Theconductive layers consisting of barrier layer 4, seed layer 5, andelectroplated metal layer 6 were separated by the chemical mechanicalpolishing to obtain an interconnect structure.

Then, on the flat surface, an insulating layer (not shown) of SiN or thelike was coated to prevent the diffusion of copper, and in addition aninsulating layer (not shown) of SiO₂ or the like is deposited. Theinsulating film (SiO₂ film) and the insulating layer (SiN layer) on theaforementioned filled copper film may be selectively removed by dryetching to form an interconnection structure having a plurality of viasas shown in FIG. 1A.

Moreover, on the thus obtained interconnection structure, the stepsshown in FIGS. 1B, 1C and 1D may be repeated on the to produce asemiconductor integrated circuit device having multi-layer fine patterninterconnection structure.

The semiconductor integrated circuit devices produced as described aboveaccording to the present invention have neither void, nor seam in thecopper film filled in the vias 3 which are the key to the constructionof the multi-layer fine pattern interconnection system. Therefore, thesemiconductor integrated circuit devices having a highly reliablemulti-layer interconnection structure can be reproducibly produced athigh yield.

EXAMPLE 3

FIG. 2 is for explaining the process for production of a semiconductorintegrated circuit device having a plurality of semiconductor circuitelement areas (not shown) formed therein. It shows an example where thepresent invention is applied to fill the inside of features for forminginterlayer connections connecting a plurality of interconnection layersat different levels, or therebetween, with copper, respectively. FIGS.2A, 2B, 2C and 2D show a crosssectional view of a major part of thedevice at each step of the process for producing the device.

As shown in FIG. 2A, a substrate 1 has first interconnection layer (notshown) on an insulating layer which is coated on the silicon wafer of φ200 mm which has a plurality of semiconductor circuit element areas (notshown) formed therein in the same manner as in Example 2, said firstinterconnection layer being connected to said plurality of semiconductorcircuit element areas. Insulating interlayers 8 and 2 of SiO₂ or thelike, each having a thickness of 0.5 μm were deposited on the topsurface of the substrate.

In these insulating interlayers, there is provided vias 3, forconnecting between interconnection layers, having a stairs typecross-section through the insulating layers 8 and 2 and having a highaspect ratio which consists of a via having φ 0.25 μm and a depth of 1μm and having the bottom in contact with the top surface of said firstinterconnection layer to expose the top surface therein, and a trench orvia having φ 0.25 μm and a depth of 0.5 μm terminating at the surface ofthe insulating layer 8, both vias being in conjunction with each otherto form said stairs type. At a location apart from the vias, there isalso provided in the insulating layer 2 a trench 7, for forming narrowand long interconnection extending on the surface of the insulatinglayer 2, having a high aspect ratio such as width 0.25 μm and a depth of0.5 μm and having the bottom on the insulating layer 8. Thus, theprovision in the insulating layers of the narrow and long trench 7 forforming interconnection, a plurality of openings having differentdepths, one of which is a continuous opening having a different depthdifferentiates this Example from Example 2 described above.

The thus produced interconnect structure is provided with a barrierlayer 4 and a seed layer 5 (FIG. 2B) as in Example 2, and further acopper layer 6 is plated on the seed layer 5 using the copperelectroplating bath of the present invention (FIG. 2C). The metal layerson the surface of the insulating layer 2 were removed by a CMP techniqueto produce a flat insulating surface at the same level as the surfacesof the copper layers 11 and 12 which were filled in the features 3 and 7(FIG. 2D).

Similarly to Example 2, the substrate after the step shown in FIG. 2Cwas completed was removed from the copper electroplating bath as asample and processed with FIB. The cross-sections of 100 vias 3 and 100trenches 7 were observed by SEM. As a result, it was found that neithervoid, nor seam was observed and the openings were perfectly filled withcopper.

As a result of observations on the process of the growth of plated filmswithin a short period of plating time, all the features had a higherfilm thickness at the bottom than that at the corner of the features. Ithas been found, therefore, that plated copper 6 were depositedproceeding preferentially from the bottoms as described with referenceto FIG. 3. Moreover, it was confirmed that the plated copper 6 weredeposited preferentially from the deepest bottoms of the features.Slight irregularities appeared to be produced on the surfaces of theinterconnection structure as a whole. It was confirmed that they have noproblem as they could be made flat by CMP to form flat major surfaceswith good reproducibility as shown in FIG. 2D.

It has been found from the foregoing that even when there are aplurality of features having different depths, or a plurality offeatures having different opening diameters, or features having asequential stairs type bottom as shown in FIG. 2A, they can be filledreproducibly with copper at a high yield without generating either voidor seam as in Example 2.

Large scale integrated circuits (LSIS) will be required to load anincreasingly larger number of complicated circuit function blocks on onesemiconductor substrate. Such LSIs will require a multi-layer finepattern interconnection structure which is produced with copper layersfilled by plating in a plurality of features having different depths andshapes as described in the present Example 3 in relation to the processof production and the configuration of circuits. Application of thepresent invention allows high reliability LSIs to be produced in largescale at a high yield.

According to the present invention, the inside of features can bereproducibly filled with copper without apertures such as voids andseams by allowing copper plating to proceed preferentially from thebottoms of the features. The possibility of forming fine vias andtrenches not having any apertures such as voids and seams can improvethe reliability of high density semiconductor integrated circuit deviceshaving fine interconnections filled with copper and the yield of theproduction thereof.

The following embodiments are disclosed in relation to the abovedescription:

(1) A copper electroplating bath comprising a solution containing copperions and electrolyte(s) with an addition of cyanine dye(s).

(2) A copper electroplating bath comprising a solution containing copperions and electrolyte(s) with an addition of indolium compound(s).

(3) A copper electroplating bath comprising a solution containing copperions and electrolyte(s) with an addition of at least one of thecompounds represented by the following general formula (I):

where X⁻ is an anion, and n is 0, 1, 2, or 3.

(4) The copper electroplating bath according to above items (1) to (3),wherein comprising said copper electroplating bath with a furtheraddition of one or more of polyethers, organic sulfur compounds andhalide ions.

(5) The copper electroplating bath according to above items (1) to (4),wherein at least one or more of said cyanine dyes, indolium compoundsand the compounds of the general formula (I) is added at a concentrationof 1 to 15 mg/L.

(6) A process for producing a semiconductor integrated circuit devicecharacterized in that said process comprising providing an insulatinglayer having features on the top of the major surface of a semiconductorwafer which has a plurality of circuit element areas formed, depositinga barrier metal layer and a seed metal layer on the bottoms and the sidesurfaces of said features and on the top surface of said insulatinglayer, and filling the inside of said features with copper byelectroplating with the copper electroplating bath according to any oneof above items (1) to (5).

1. A copper electroplating solution containing copper ions, at least oneelectrolyte, and at least one cyanine dye, wherein said at least onecyanine dye suppresses an electroplating reaction during use of thecopper electroplating solution for electroplating, and said at least onecyanine dye is present in the solution in a concentration of 1-15 mg/L.2. A copper electroplating solution containing copper ions, at least oneelectrolyte, and at least one indolium compound, wherein said at leastone indolium compound suppresses an electroplating reaction during useof the copper electroplating solution for electroplating, and said atleast one indolium compound is present in the solution in aconcentration of 1-15 mg/L.
 3. A copper electroplating solutioncontaining copper ions, at least one electrolyte and at least one of thecompounds represented by the following general formula

where X⁻ is an anion, and n is 0, 1, 2, or 3, wherein said at least oneof the compounds represented by the general formula (I) suppresses anelectroplating reaction during use of the copper electroplating solutionfor electroplating, and is present in the solution in a concentration of1-15 mg/L.
 4. The copper electroplating bath according to claim 1,further including at least one selected from the group consisting ofpolyether, organic sulfur compound, and halide ion, wherein the bathincludes a polyether when it includes said halide ion.
 5. The copperelectroplating bath according to claim 2, further including at least oneselected from the group consisting of polyether, organic sulfurcompound, and halide ion, wherein the bath includes a polyether when itincludes said halide ion.
 6. The copper electroplating bath according toclaim 3, further including at least one selected from the groupconsisting of polyether, organic sulfur compound, and halide ion,wherein the bath includes a polyether when it includes said halide ion.7. A process for producing a semiconductor integrated circuit devicecomprising providing an insulating layer having features on the top ofthe major surface of a semiconductor wafer which has a plurality ofcircuit element areas formed, depositing a barrier metal layer and aseed metal layer on the bottoms and the side surfaces of said featuresand on the top surface of said insulating layer, and filling the insideof said features with copper by electroplating with the copperelectroplating solution according to claim
 1. 8. A process for producinga semiconductor integrated circuit device comprising providing aninsulating layer having features on the top of the major surface of asemiconductor wafer which has a plurality of circuit element areasformed, depositing a barrier metal layer and a seed metal layer on thebottoms and the side surfaces of said features and on the top surface ofsaid insulating layer, and filling the inside of said features withcopper by electroplating with the copper electroplating solutionaccording to claim
 2. 9. A process for producing a semiconductorintegrated circuit device comprising providing an insulating layerhaving features on the top of the major surface of a semiconductor waferwhich has a plurality of circuit element areas formed, depositing abarrier metal layer and a seed metal layer on the bottoms and the sidesurfaces of said features and on the top surface of said insulatinglayer, and filling the inside of said features with copper byelectroplating with the copper electroplating solution according toclaim
 3. 10. A copper electroplating solution containing copper ions, atleast one electrolyte, and an additive selected from the groupconsisting of (a) cyanine dyes, (b) indolium compounds, and (c)compounds represented by the following general formula (I):

where X⁻ is an anion, and n is 0, 1, 2 or 3, wherein said additivesuppresses an electroplating reaction during use of the copperelectroplating solution for electroplating, and is present in thesolution in a concentration of 1-15 mg/L.
 11. The copper electroplatingbath according to claim 10, further including a least one selected fromthe group consisting of polyether, organic sulfur compound, and halideion, wherein the bath includes a polyether when it includes said halideion.
 12. A process for producing a semiconductor integrated circuitdevice comprising providing an insulating layer having features on thetop of the major surface of a semiconductor wafer which has a pluralityof circuit element areas formed, depositing a barrier metal layer and aseed metal layer on the bottoms and the side surfaces of said featuresand on the top surface of said insulating layer, and filling the insideof said features with copper by electroplating with the copperelectroplating solution according to claim
 10. 13. The copperelectroplating solution according to claim 10, wherein said additive isconsumed as the electroplating reaction proceeds, and a diffusion ratethereof is lower than a rate of reaction of the additives during the useof the copper electroplating solution for electroplating.
 14. The copperelectroplating solution according to claim 3, wherein said at least oneof the compounds represented by the general formula (I) is consumed asthe electroplating reaction proceeds, and a diffusion rate thereof islower than the rate of reaction thereof during the use of the copperelectroplating solution for electroplating.
 15. The copperelectroplating solution according to claim 6, further containing saidpolyether.
 16. The copper electroplating solution according to claim 15,wherein said polyether is selected from the group consisting ofpolyethylene glycols, polypropylene glycols and polyoxypropyleneglycols, having an average molecular weight of 1000 to 10,000.
 17. Thecopper electroplating solution according to claim 6, further containingsaid organic sulfur compound.
 18. The copper electroplating solutionaccording to claim 17, wherein said organic sulfur compound is selectedfrom the group consisting of 3-mercapto-1-propanesulfonic acid,2-mercapto ethane sulfonic acid, bis (4-sulfobutyl) disulfide, bis(3-sulfopropyl) disulfide, bis (2-sulfaethyl) disulfide and bis(p-sulfophenyl) disulfide.
 19. A process for producing a semiconductorintegrated circuit device comprising providing an insulating layerhaving features on the top of the major surface of a semiconductor waferwhich has a plurality of circuit element areas formed, depositing abarrier metal layer and a seed metal layer on the bottoms and the sidesurfaces of said features and on the top surface of said insulatinglayer, and filling the inside of said features with copper byelectroplating with the copper electroplating solution according toclaim 3, wherein said at least one of the compounds represented by thegeneral formula (I) is consumed as the electroplating reaction proceeds,and has a diffusion rate lower than a rate of reaction thereof duringthe process.
 20. A process for producing a semiconductor integratedcircuit device comprising providing an insulating layer having featureson the top of the major surface of a semiconductor wafer which has aplurality of circuit element areas formed, depositing a barrier metallayer and a seed metal layer on the bottoms and the side surfaces ofsaid features and on the top surface of said insulating layer, andfilling the inside of said features with copper by electroplating withthe copper electroplating solution according to claim 10, wherein saidadditive is consumed as the electroplating reaction proceeds, and has adiffusion rate lower than a rate of reaction thereof during the process.21. The process according to claim 9, wherein concentration of said atleast one of the compounds represented by the general formula (I) in theelectroplating solution, at said bottoms of said features, during theprocess, is less than that at a top of said features.
 22. The processaccording to claim 12, wherein concentration of said additive in theelectroplating solution, at said bottoms of said features, during theprocess, is less than that at a top of said features.
 23. The copperelectroplating solution according to claim 2, wherein said at least oneindolium compound is consumed as the electroplating reaction proceeds,and a diffusion rate thereof is lower than a rate of reaction thereofduring use of the copper electroplating solution for electroplating. 24.The copper electroplating solution according to claim 1, wherein said atleast one cyanine dye is consumed as the electroplating reactionproceeds, and a diffusion rate thereof is lower than a rate of reactionthereof during use of the copper electroplating solution forelectroplating.